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ST72321BXXX-AUTO Datasheet(PDF) 60 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 60 Page - STMicroelectronics |
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60 / 247 page  Interrupts ST72321Bxxx-Auto 60/247 7.5.2 Interrupt software priority registers (ISPRx) These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read only. These four registers contain the interrupt software priority of each interrupt vector. ● Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following Table 17. ● Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. ● Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h). The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Table 16. Interrupt software priority levels Interrupt software priority Level I1 I0 Level 0 (main) Low High 10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable(1)) 1. TLI, TRAP and RESET events can interrupt a level 3 program. 11 ISPRx Reset value: 1111 1111 (FFh) 76543 210 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 1111 I1_13 I0_13 I1_12 I0_12 Table 17. Interrupt priority bits Vector address ISPRx bits FFFBh-FFFAh I1_0 and I0_0 bits(1) 1. Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. FFF9h-FFF8h I1_1 and I0_1 bits ... ... FFE1h-FFE0h I1_13 and I0_13 bits |
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