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ST72321BXXX-AUTO Datasheet(PDF) 63 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 63 Page - STMicroelectronics |
63 / 247 page ![]() ST72321Bxxx-Auto Interrupts 63/247 To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Figure 21. External interrupt control bits IS10 IS11 EICR SENSITIVITY CONTROL PBOR.3 PBDDR.3 IPB BIT PB3 ei2 INTERRUPT SOURCE PORT B [3:0] INTERRUPTS PB3 PB2 PB1 PB0 IS10 IS11 EICR SENSITIVITY CONTROL PBOR.7 PBDDR.7 PB7 ei3 INTERRUPT SOURCE PORT B [7:4] INTERRUPTS PB7 PB6 PB5 PB4 IS20 IS21 EICR SENSITIVITY CONTROL PAOR.3 PADDR.3 IPA BIT PA3 ei0 INTERRUPT SOURCE PORT A [3:0] INTERRUPTS PA3 PA2 PA1 PA0 IS20 IS21 EICR SENSITIVITY CONTROL PFOR.2 PFDDR.2 PF2 ei1 INTERRUPT SOURCE PORT F [2:0] INTERRUPTS PF2 PF1 PF0 |
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