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ST72321BXXX-AUTO Datasheet(PDF) 70 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 70 Page - STMicroelectronics |
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70 / 247 page  Power saving modes ST72321Bxxx-Auto 70/247 8.4.1 Active Halt mode Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section 12.3: ART registers for more details on the MCCSR register). The MCU can exit Active Halt mode on reception of an external interrupt, MCC/RTC interrupt or a RESET. When exiting Active Halt mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 26). When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in Active Halt mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering Active Halt mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. Caution: When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining tDELAY period. Figure 25. Active Halt timing overview 1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET. Table 26. MCC/RTC low power mode selection MCCSR OIE bit Power saving mode entered when HALT instruction is executed 0Halt 1 Active Halt HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY(1) RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR ACTIVE [MCCSR.OIE = 1] |
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