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ST72321BXXX-AUTO Datasheet(PDF) 71 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 71 Page - STMicroelectronics |
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71 / 247 page  ST72321Bxxx-Auto Power saving modes 71/247 Figure 26. Active Halt mode flowchart 1. Peripheral clocked with an external clock source can still be active. 2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. 8.4.2 Halt mode The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see Chapter 11: Main clock controller with real-time clock and beeper (MCC/RTC) for more details on the MCCSR register). The MCU can exit Halt mode on reception of either a specific interrupt (see Table 19: Interrupt mapping on page 62) or a RESET. When exiting Halt mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28). When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the HALT INSTRUCTION RESET Y N N Y CPU OSCILLATOR PERIPHERALS(1) I[1:0] BITS ON OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX(2) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX(2) ON 256 OR 4096 CPU CLOCK CYCLE DELAY (MCCSR.OIE = 1) INTERRUPT |
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