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ST72321BXXX-AUTO Datasheet(PDF) 72 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 72 Page - STMicroelectronics |
72 / 247 page ![]() Power saving modes ST72321Bxxx-Auto 72/247 ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’ option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash configuration on page 228 for more details). Figure 27. Halt timing overview HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [MCCSR.OIE = 0] |
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