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ST72321BXXX-AUTO Datasheet(PDF) 75 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 247 page  ST72321Bxxx-Auto I/O ports 75/247 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O port contains up to eight pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 Functional description Each port has two main registers: ● Data Register (DR) ● Data Direction Register (DDR) and one optional register: ● Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers (bit X corresponding to pin X of the port). The same correspondence is used for the DR register. The following description takes into account the OR register (for specific ports which do not provide this register refer to Section 9.3: I/O port implementation on page 79). The generic I/O block diagram is shown in Figure 29. 9.2.1 Input modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note: 1 Writing the DR register modifies the latch value but does not affect the pin status. 2 When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. |
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