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ST72321BXXX-AUTO Datasheet(PDF) 85 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 85 Page - STMicroelectronics |
85 / 247 page ![]() ST72321Bxxx-Auto Watchdog timer (WDG) 85/247 10.5 Low power modes 10.6 Hardware watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 21.1.1: Flash configuration on page 228. 10.7 Using Halt mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled: Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected WDG reset immediately after waking up the microcontroller. 10.8 Interrupts None. Table 34. Effect of low power modes on WDG Mode Effect Slow No effect on Watchdog Wait No effect on Watchdog Halt OIE bit in MCCSR register WDGHALT bit in Option Byte 00 No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.7 below. 0 1 A reset is generated. 1x No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks. |
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