ST72321BXXX-AUTO datasheet(3/247 Pages) STMICROELECTRONICS

Part #	ST72321BXXX-AUTO

Description	8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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3 / 247 page

ST72321Bxxx-Auto

Contents

3/247

6

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.3

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.4

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.5

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5.2

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5.3

External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.5.4

Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 48

6.5.5

Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.6.1

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.6.2

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.6.3

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.6.4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.6.5

System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 53

7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.2

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.3

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.4

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.5

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.5.1

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.5.2

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 60

7.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.6.1

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.6.2

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 64

8

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.4

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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