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ST72321BXXX-AUTO Datasheet(PDF) 42 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 247 page  Central processing unit (CPU) ST72321Bxxx-Auto 42/247 These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See Chapter 7: Interrupts on page 55 for more details. 5.3.5 Stack pointer (SP) register 7 1Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. 0 C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Table 7. Interrupt management bits Bit Name Function 5 I1 Interrupt Software Priority 1 The combination of the I1 and I0 bits gives the current interrupt software priority. 3 I0 Interrupt Software Priority 0 The combination of the I1 and I0 bits gives the current interrupt software priority. Table 8. Interrupt software priority selection Interrupt software priority Level I1 I0 Level 0 (main) Low High 10 Level 1 01 Level 2 00 Level 3 (= interrupt disable) 1 1 Table 6. Arithmetic management bits (continued) Bit Name Function SP Reset value: 01 FFh 15 14 13 12 11 10 987 65432 10 00000 001 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 RW RW RW RW RW RW RW RW |
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