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ST72321BXXX-AUTO Datasheet(PDF) 49 Page - STMicroelectronics |
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ST72321BXXX-AUTO Datasheet(HTML) 49 Page - STMicroelectronics |
49 / 247 page ![]() ST72321Bxxx-Auto Supply, reset and clock management 49/247 Figure 13. RESET sequences 6.6 System integrity management (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. 6.6.1 Low voltage detector (LVD) The low voltage detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power- on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD reset circuitry generates a reset when VDD is below: –VIT+ when VDD is rising –VIT- when VDD is falling The LVD function is illustrated in Figure 14. The voltage threshold can be configured by option byte to be low, medium or high. VDD RUN RESET PIN EXTERNAL WATCHDOG Active Phase VIT+(LVD) VIT-(LVD) th(RSTL)in tw(RSTL)out RUN th(RSTL)in Active WATCHDOG UNDERFLOW tw(RSTL)out RUN RUN RUN RESET RESET SOURCE SHORT EXT. RESET LVD RESET LONG EXT. RESET WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH tw(RSTL)out Phase Active Phase Active Phase DELAY |
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