M32C83T datasheet(112/527 Pages) RENESAS

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10. Interrupts

)

(

Undefined Instruction (UND Instruction)

Overflow (INTO Instruction)

BRK Instruction

BRK2 Instruction(2)

INT Instruction

Software

(Non-Maskable Interrupt)

Hardware

Interrupt

_______

NMI

Watchdog Timer

Oscillation Stop Detect

Single-Step(2)

Address Match

DMACII

Special

(Non-Maskable Interrupt)

Peripheral Function(1)

(Maskable Interrupt)

NOTES:

1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.

2. Do not use this interrupt. For development support tools only.

10. Interrupts

10.1 Types of Interrupts

Figure 10.1 shows types of interrupts.

Figure 10.1 Interrupts

• Maskable Interrupt

The I flag enables or disables an interrupt.

The interrupt priority order based on interrupt priority level can be changed.

• Non-maskable Interrupt

The I flag does not enable nor disable an interrupt .

The interrupt priority order based on interrupt priority level cannot be changed.

10.2 Software Interrupts

Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable inter-

rupts.

10.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt occurs when the UND instruction is executed.

10.2.2 Overflow Interrupt

The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic

operation) and the INTO instruction is executed.

Instructions to set the O flag are :

ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX

10.2.3 BRK Interrupt

The BRK interrupt occurs when the BRK instruction is executed.

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