M32C83T datasheet(123/527 Pages) RENESAS

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10. Interrupts

)

(

10.6.4 Interrupt Response Time

Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt

generation and the execution of the first instruction in an interrupt service routine. An interrupt response

time includes the period between an interrupt request generation and the completed execution of an in-

struction ((a) in Figure 10.6) and the period required to perform an interrupt sequence ((b) in Figure 10.6).

Figure 10.6 Interrupt Response Time

Time (a) varies depending on the instruction being executed. The DIV instruction requires the longest

time (a); 40 cycles when an immediate value or register is set as the divisor .

When the divisor is a value in the memory, the following value is added.

• Normal addressing

: 2 + X

• Index addressing

: 3 + X

• Indirect addressing

: 5 + X + 2Y

• Indirect index addressing

: 6 + X + 2Y

X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores

indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be

doubled.

Table 10.4 lists time (b).

(a) Period between an interrupt request generation and the completed execution of an instruction.

(b) Period required to perform an interrupt sequence.

(a)

(b)

Time

Instruction

Interrupt response time

Instruction in an

interrupt routine

Interrupt sequence

Interrupt request is acknowledged

Interrupt request is generated

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