H838532H datasheet(251/508 Pages) RENESAS

251 / 508 page

Section 9 Timers

Rev. 1.00 May 30, 2008 Page 231 of 484

REJ09B0436-0100

Bits 2 to 0: Clock select L (CKSL2 to CKSL0)

Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external

event input.

Bit 2

CKSL2

Bit 1

CKSL1

Bit 0

CKSL0

Description

Counting on external event (TMIF) rising/falling edge*

(initial value)

Use prohibited

Internal clock: Counting on

φ/32

Internal clock: Counting on

φ/16

Internal clock: Counting on

φ/4

Internal clock: Counting on

φw/4

Note:

External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For

details, see (1) IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control

Registers.

Note that the timer F counter may increment if the setting of IRQ3 in port mode register

1 (PMR1) is changed from 0 to 1 while the TMIF pin is low in order to change the TMIF

pin function.

(4) Timer Control/Status Register F (TCSRF)

OVFH

CMFL

OVIEL

CCLRL

CMFH

OVIEH

CCLRH

OVFL

6543210

0000000

R/W*

R/W

R/W*

R/W

R/W*

Note: *

Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.

Bit

Initial value

Read/Write

TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,

and compare match flag setting, and controls enabling of overflow interrupt requests.

TCSRF is initialized to H'00 upon reset.

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