H838532H datasheet(318/508 Pages) RENESAS

318 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 298 of 484

REJ09B0436-0100

Description

Bit 1

CKE1

Bit 0

CKE0

Communication Mode

Clock Source

SCK

3x Pin Function

Asynchronous

Internal clock

I/O port*

Synchronous

Internal clock

Serial clock output*

Asynchronous

Internal clock

Clock output*

Synchronous

Reserved

Asynchronous

External clock

Clock input*

Synchronous

External clock

Serial clock input

Asynchronous

Reserved

Synchronous

Reserved

Notes: 1. Initial value

2. A clock with the same frequency as the bit rate is output.

3. Input a clock with a frequency 16 times the bit rate.

10.2.7

Serial Status Register (SSR)

Bit

Initial value

Read/Write

Note: * Only a write of 0 for flag clearing is possible.

TDRE

R/(W)

RDRF

R/(W)

OER

R/(W)

FER

R/(W)

PER

R/(W)

MPBT

R/W

TEND

MPBR

***

SSR is an 8-bit register containing status flags that indicate the operational status of SCI3.

SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,

RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.

Bits TEND and MPBR are read-only bits, and cannot be modified.

SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.

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