HD6432351 datasheet(518/1025 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 484 of 988

REJ09B0330-0300

Input Capture/Compare Match Interrupt

An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1

by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt

request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match

interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

Overflow Interrupt

An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to

1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing

the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel.

Underflow Interrupt

An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to

1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing

the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.

10.5.2

DTC/DMAC Activation

DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For

details, see section 8, Data Transfer Controller (DTC).

A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

DMAC Activation

The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.

For details, see section 7, DMA Controller (DMAC).

In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC

activation sources, one for each channel.

HD6432351 Datasheet(PDF) 518 Page - Renesas Technology Corp