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HD6432351 Datasheet(PDF) 716 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 716 Page - Renesas Technology Corp |
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716 / 1025 page ![]() Section 19 Clock Pulse Generator Rev. 3.00 Sep 15, 2006 page 682 of 988 REJ09B0330-0300 External Clock The external clock signal should have the same frequency as the system clock ( φ). Table 19.4 and figure 19.6 show the input conditions for the external clock. Table 19.4 External Clock Input Conditions VCC = 2.7 V to 5.5 V VCC = 5.0 V ±10% Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 40 — 20 — ns Figure 19.6 External clock input high pulse width tEXH 40 — 20 — ns External clock rise time tEXr — 10 — 5 ns External clock fall time tEXf — 10 — 5 ns tCL 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz Figure 21.4 Clock low pulse width level 80 — 80 — ns φ < 5 MHz tCH 0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz Clock high pulse width level 80 — 80 — ns φ < 5 MHz tEXH tEXL tEXr tEXf VCC × 0.5 EXTAL Figure 19.6 External Clock Input Timing |
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