HD6432351 datasheet(734/1025 Pages) RENESAS

Part #	HD6432351

Description	16-Bit Single-Chip Microcomputer

PDF	1025 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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734 / 1025 page

Section 20 Power-Down Modes

Rev. 3.00 Sep 15, 2006 page 700 of 988

REJ09B0330-0300

20.8

φφφφ Clock Output Disabling Function

Output of the

φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the

corresponding port. When the PSTOP bit is set to 1, the

φ clock stops at the end of the bus cycle,

and

φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0,

φ clock output is disabled and input port mode is set.

Table 20.5 shows the state of the

φ pin in each processing state.

Table 20.5

φφφφ Pin State in Each Processing State

DDR

PSTOP

—

Hardware standby mode

High impedance

Software standby mode

High impedance

Fixed high

Sleep mode

High impedance

φ output

Fixed high

Normal operating state

High impedance

φ output

Fixed high

HD6432351 Datasheet(PDF) 734 Page - Renesas Technology Corp