 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HD6432351 Datasheet(PDF) 881 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432351 Datasheet(HTML) 881 Page - Renesas Technology Corp |
|
|
881 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 847 of 988 REJ09B0330-0300 MCR—Memory Control Register H'FED6 Bus Controller 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W 0 RLW0 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W Bit Initial value Read/Write : : : TP Cycle Control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted Burst Access Enable 0 1 Burst disabled (always full access) RAS/CS Down Mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected 2-CAS Method Select 0 1 16-bit DRAM space selected 8-bit DRAM space selected Multiplex Shift Count 0 1 8-bit shift 9-bit shift 10-bit shift — 0 1 0 1 Refresh Cycle Wait Control 0 1 No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted 0 1 0 1 For DRAM space access, access in fast page mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
