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HD6432351 Datasheet(PDF) 216 Page - Renesas Technology Corp

Part # HD6432351
Description  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 Datasheet(HTML) 216 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev. 3.00 Sep 15, 2006 page 182 of 988
REJ09B0330-0300
(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 6.32 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
T1
Address bus
φ
RD
Bus cycle A
Data bus
T2
T3
T1
T2
Bus cycle B
Long output
floating time
Data
collision
T1
Address bus
φ
RD
Bus cycle A
Data bus
T2
T3
TI
T1
Bus cycle B
T2
HWR
HWR
CS (area A)
CS (area B)
CS (area A)
CS (area B)
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6.32 Example of Idle Cycle Operation (2)



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