HD6432351 datasheet(226/1025 Pages) RENESAS

226 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 192 of 988

REJ09B0330-0300

6.11.3

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific times at which each bus master can relinquish the bus.

CPU

The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or

DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for

transfer of the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations. See appendix A.5, Bus States during Instruction Execution, for timings at

which the bus is not transferred.

• If the CPU is in sleep mode, it transfers the bus immediately.

DTC

The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC can release the bus after a vector read, a register information read (3 states), a single data

transfer, or a register information write (3 states). It does not release the bus during a register

information read (3 states), a single data transfer, or a register information write (3 states).

DMAC

The DMAC sends the bus arbiter a request for the bus when an activation request is generated.

In the case of an external request in short address mode or normal mode, and in cycle steal mode,

the DMAC releases the bus after a single transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after

completion of a transfer.

HD6432351 Datasheet(PDF) 226 Page - Renesas Technology Corp