HD6432351 datasheet(320/1025 Pages) RENESAS

320 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 286 of 988

REJ09B0330-0300

(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

[2]

[1]

Note: The lower word of MAR is the updated value after the operation in [1].

CPU longword read

DMA transfer cycle

MAR upper

word read

MAR lower

word read

DMA read

DMA write

DMA internal

address

DMA control

DMA register

operation

Transfe

source

Transfer

destination

Idle

Read

Write

Idle

Figure 8.41 Contention between DMAC Register Update and CPU Read

Module Stop

When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is

entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled.

This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)

• TEND pin enable (TEE = 1)

• DACK pin enable (FAE = 0 and SAE = 1)

Medium-Speed Mode

When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-

detected.

In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting

modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt

source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is

HD6432351 Datasheet(PDF) 320 Page - Renesas Technology Corp

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