HD6432142 datasheet(395/1177 Pages) RENESAS

395 / 1177 page

Section 12 8-Bit Timers

Rev. 4.00 Sep 27, 2006 page 351 of 1130

REJ09B0327-0400

TCR

STCR

Bit 2 Bit 1 Bit 0

Bit 1

Bit 0

Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description

—

Clock input disabled

(Initial value)

—

Counted on

φ internal clock source

010

—

φ/2 internal clock source, counted on the falling edge

011

—

φ/4 internal clock source, counted on the falling edge

—

Clock input disabled

—

Clock input disabled

(Initial value)

001

—

φ/4 internal clock source, counted on the falling edge

010

—

φ/256 internal clock source, counted on the falling

edge

011

—

φ/2048 internal clock source, counted on the falling

edge

—

Clock input disabled

Common 1

—

External clock source, counted at rising edge

—

External clock source, counted at falling edge

—

External clock source, counted at both rising and

falling edges

Note:

If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the

TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this

setting.

HD6432142 Datasheet(PDF) 395 Page - Renesas Technology Corp

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