HD6432142 datasheet(434/1177 Pages) RENESAS

434 / 1177 page

Section 13 Timer Connection

Rev. 4.00 Sep 27, 2006 page 390 of 1130

REJ09B0327-0400

Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and

phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to

determine whether the input signal is positive or negative, then maintain the IVI signal at positive

phase by modifying TCONRI.

Bit 0

IVI

Description

The IVI signal is low

The IVI signal is high

13.2.5

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit

timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt

and enter module stop mode. See section 25.5., Module Stop Mode, for details.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode.

MSTPCRH

Bit 5

MSTP13

Description

FRT module stop mode is cleared

FRT module stop mode is set

(Initial value)

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