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HD6432142 Datasheet(PDF) 672 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 672 Page - Renesas Technology Corp |
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672 / 1177 page ![]() Section 20 A/D Converter Rev. 4.00 Sep 27, 2006 page 628 of 1130 REJ09B0327-0400 20.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t D after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D conversion timing. Table 20.4 indicates the A/D conversion time. As indicated in figure 20.5, the A/D conversion time includes t D and the input sampling time. The length of t D varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 20.4. In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) (2) tD tSPL tCONV Address φ Write signal Input sampling timing ADF Legend: (1) : ADCSR write cycle (2) : ADCSR address tD : A/D conversion start delay time tSPL : Input sampling time tCONV : A/D conversion time Figure 20.5 A/D Conversion Timing |
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