HD6432142 datasheet(702/1177 Pages) RENESAS

702 / 1177 page

Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)

Rev. 4.00 Sep 27, 2006 page 658 of 1130

REJ09B0327-0400

Automatic SCI Bit Rate Adjustment

Start

bit

Stop

bit

Low period (9 bits) measured (H'00 data)

High period

(1 or more bits)

Figure 22.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment

When boot mode is initiated, this group MCU measures the low period of the asynchronous SCI

communication data (H'00) transmitted continuously from the host. The SCI transmit/receive

format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of

the transmission from the host from the measured low period, and transmits one H'00 byte to the

host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end

indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception

cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.

Depending on the host’s transmission bit rate and the MCU’s system clock frequency, there will

be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation,

the host’s transfer bit rate should be set to (2400, 4800, or 9600) bps.

Table 22.7 shows typical host transfer bit rates and system clock frequencies for which automatic

adjustment of the MCU’s bit rate is possible. The boot program should be executed within this

system clock range.

Table 22.7

System Clock Frequencies for which Automatic Adjustment of This Group Bit

Rate Is Possible

Host Bit Rate

System Clock Frequency for which Automatic Adjustment

of This Group Bit Rate Is Possible

9600 bps

8 MHz to 20 MHz

4800 bps

4 MHz to 20 MHz

2400 bps

2 MHz to 18 MHz

HD6432142 Datasheet(PDF) 702 Page - Renesas Technology Corp