HD6432142 datasheet(758/1177 Pages) RENESAS

758 / 1177 page

Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)

Rev. 4.00 Sep 27, 2006 page 714 of 1130

REJ09B0327-0400

Table 23.9

Software Protection

Functions

Item

Description

Program

Erase

SWE bit protection

• Clearing the SWE bit to 0 in FLMCR1 sets the

program/erase-protected state for all blocks.

(Execute in on-chip RAM or external memory.)

Yes

Block specification

protection

• Erase protection can be set for individual blocks

by settings in erase block registers 1 and 2

(EBR1, EBR2).

• Setting EBR1 and EBR2 to H'00 places all

blocks in the erase-protected state.

—

Yes

23.8.3

Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in

FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2

settings are retained, but program mode or erase mode is aborted at the point at which the error

occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,

PV and EV bit setting is enabled, and a transition can be made to verify mode.

FLER bit setting conditions are as follows:

• When flash memory is read during programming/erasing (including a vector read or instruction

fetch)

• Immediately after exception handling (excluding a reset) during programming/erasing

• When a SLEEP instruction (including software standby, sleep, subactive, subsleep and watch

mode) is executed during programming/erasing

• When the bus is released during programming/erasing

Error protection is released only by a reset and in hardware standby mode.

Figure 23.14 shows the flash memory state transition diagram.

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