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HD6432142 Datasheet(PDF) 782 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 782 Page - Renesas Technology Corp |
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782 / 1177 page  Section 24 Clock Pulse Generator Rev. 4.00 Sep 27, 2006 page 738 of 1130 REJ09B0327-0400 external clock output settling delay time (t DEXT). As the clock signal output is not fixed during the t DEXT period, the reset signal should be driven low to maintain the reset state. Table 24.5 External Clock Output Settling Delay Time Conditions: V CC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output settling delay time t DEXT * 500 — µs Figure 24.7 Note: * t DEXT includes RES pulse width (tRESW). tDEXT* RES (internal or external) EXTAL STBY VCC 2.7V VIH φ Note: * tDEXT includes RES pulse width (tRESW). Figure 24.7 External Clock Output Settling Delay Timing |
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