HD6432142 datasheet(797/1177 Pages) RENESAS

797 / 1177 page

Section 25 Power-Down State

Rev. 4.00 Sep 27, 2006 page 753 of 1130

REJ09B0327-0400

25.3

Medium-Speed Mode

When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode

changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU

operates on the operating clock (

φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits.

The bus master other than the CPU (the DTC) also operates in medium-speed mode. On-chip

supporting modules other than the bus masters always operate on the high-speed clock (

φ).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if

φ/4 is selected as the operating clock, on-chip

memory is accessed in 4 states, and internal I/O registers in 8 states.

Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR

are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt,

medium-speed mode is restored.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in

LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0, a transition is made to software

standby mode. When software standby mode is cleared by an external interrupt, medium-speed

mode is restored.

When the

RES pin is driven low, a transition is made to the reset state, and medium-speed mode is

cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

Figure 25.2 shows the timing for transition to and clearance of medium-speed mode.

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