HD6432142 datasheet(899/1177 Pages) RENESAS

899 / 1177 page

Section 26 Electrical Characteristics

Rev. 4.00 Sep 27, 2006 page 855 of 1130

REJ09B0327-0400

Condition A

Condition B

20 MHz

10 MHz

Item

Symbol Min

Max

Min

Max

Unit

Test

Conditions

TMR

Timer output

delay time

TMOD

—

100

Figure

26.18

Timer reset input

setup time

TMRS

—

Figure

26.20

Timer clock input

setup time

TMCS

—

Figure

26.19

Single

edge

TMCWH

1.5

—

1.5

—

cyc

Timer

clock

pulse

width

Both

edges

TMCWL

2.5

—

2.5

—

PWM,

PWMX

Pulse output

delay time

PWOD

—

100

Figure

26.21

SCI

Asynchro-

nous

Scyc

4—

—

cyc

Figure

26.22

Input

clock

cycle

Synchro-

nous

6—

—

Input clock pulse

width

SCKW

0.4

0.6

0.4

0.6

Scyc

Input clock rise

time

SCKr

—

1.5

—

1.5

cyc

Input clock fall

time

SCKf

—

1.5

—

1.5

Transmit data

delay time

(synchronous)

TXD

—

100

Figure

26.23

Receive data setup

time (synchronous)

RXS

—

100

—

Receive data hold

time (synchronous)

RXH

—

100

—

A/D

conver-

ter

Trigger input setup

time

TRGS

—

Figure

26.24

WDT

RESO output delay

time

RESD

—

100

—

200

Figure

26.25

RESO output pulse

width

RESOW

132

—

132

—

cyc

Note:

Only supporting modules that can be used in subclock operation

HD6432142 Datasheet(PDF) 899 Page - Renesas Technology Corp

HD6432142 Datasheet(HTML) 899 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL