HD6432142 datasheet(986/1177 Pages) RENESAS

986 / 1177 page

Appendix A Instruction Set

Rev. 4.00 Sep 27, 2006 page 942 of 1130

REJ09B0327-0400

8. Block Transfer Instructions

Mnemonic

Addressing Mode and

Instruction Length (Bytes)

EEPMOV EEPMOV.B

EEPMOV.W

if R4L

≠0

Repeat @ER5

→@ER6

ER5+1

→ER5

ER6+1

→ER6

R4L-1

→R4L

Until R4L=0

else next;

if R4

≠0

Repeat @ER5

→@ER6

ER5+1

→ER5

ER6+1

→ER6

R4-1

→R4

Until R4=0

else next;

—

4+2n*2

—

Operation

Condition Code

No. of

States*1

—

Notes: 1. The number of states is the number of states required for execution when the

instruction and its operands are located in on-chip memory.

2. n is the initial value set in R4L or R4.

3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

4. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

[1] 7 states when the number of saved/restored registers is 2, 9 states when 3, and 11

states when 4.

[2] Cannot be used with this LSI.

[3] Set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0.

[4] Set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0.

[5] If the result is zero, the previous value of the flag is retained; otherwise the flag is

cleared to 0.

[6] Set to 1 if the divisor is negative; otherwise cleared to 0.

[7] Set to 1 if the divisor is zero; otherwise cleared to 0.

[8] Set to 1 if the quotient is negative; otherwise cleared to 0.

[9] When EXR is valid, the number of states is increased by 1.

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