HD6432142 datasheet(1051/1177 Pages) RENESAS

1051 / 1177 page

Appendix B Internal I/O Registers

Rev. 4.00 Sep 27, 2006 page 1007 of 1130

REJ09B0327-0400

CRA—DTC Transfer Count Register A

H'EC00–H'EFFF

DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

CRAH

CRAL

Specifies the number of DTC data transfers

CRB—DTC Transfer Count Register B

H'EC00–H'EFFF

DTC

Unde-

fined

—

Bit

Initial value

Read/Write

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Specifies the number of DTC block data transfers

HICR2—Host Interface Control Register 2

H'FE80

HIF

—

IBFIE4

R/W

—

IBFIE3

R/W

—

Bit

Initial value

Slave R/W

Host R/W

Input data register full interrupt enable

—

IBFIE4

IBFIE3

Description

—

Input data register (IDR3) receive complete interrupt is disabled

Input data register (IDR4) receive complete interrupt is disabled

Input data register (IDR4) receive complete interrupt is enabled

Input data register (IDR3) receive complete interrupt is enabled

HD6432142 Datasheet(PDF) 1051 Page - Renesas Technology Corp

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