HD6432142 datasheet(1117/1177 Pages) RENESAS

1117 / 1177 page

Appendix B Internal I/O Registers

Rev. 4.00 Sep 27, 2006 page 1073 of 1130

REJ09B0327-0400

TCSR1—Timer Control/Status Register 1

H'FFEA

WDT1

OVF

R/(W)*1

WT/

R/W

TME

R/W

PSS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Clock select 2 to 0

PSS

Clock

CKS2

CKS1

CKS0

Notes: 1.

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

φSUB/2

φSUB/4

φSUB/8

φSUB/16

φSUB/32

φSUB/64

φSUB/128

φSUB/256

Reset or NMI

NMI interrupt requested

Internal reset requested

Prescaler select*

TCNT counts on a ø-based prescaler (PSM) scaled clock

TCNT counts on a øSUB-based prescaler (PSS) scaled clock

Timer enable

TCNT is initialized to H'00 and halted

TCNT counts

Timer mode select

Interval timer mode: Interval timer interrupt request (WOVI)

sent to CPU when TCNT overflows

Watchdog timer mode: Reset or NMI interrupt request sent

to CPU when TCNT overflows

Only 0 can be written, to clear the flag.

For operation control when a transition is made to power-down mode, see section 25.2.3, Timer Control/Status Register (TCSR).

Note: * When OVF is polled and the interval timer interrupt is disabled,

OVF = 1 must be read at least twice.

Overflow flag

[Clearing conditions]

• Write 0 in the TME bit

• Read TCSR when OVF = 1*, then write 0 in OVF

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

(When internal reset request generation is selected in watchdog

timer mode, OVF is cleared automatically by the internal reset.)

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