HD6432142 datasheet(225/1177 Pages) RENESAS

225 / 1177 page

Section 7 Data Transfer Controller (DTC)

Rev. 4.00 Sep 27, 2006 page 181 of 1130

REJ09B0327-0400

7.1.3

Table 7.1 summarizes the DTC registers.

Table 7.1

DTC Registers

Name

Abbreviation

R/W

Initial Value

Address*

DTC mode register A

MRA

—*

Undefined

—*

DTC mode register B

MRB

—*

Undefined

—*

DTC source address register

SAR

—*

Undefined

—*

DTC destination address register

DAR

—*

Undefined

—*

DTC transfer count register A

CRA

—*

Undefined

—*

DTC transfer count register B

CRB

—*

Undefined

—*

DTC enable registers

DTCER*

R/W

H'00

H'FEEE to H'FEF2

DTC vector register

DTVECR*

R/W

H'00

H'FEF3

Module stop control register

MSTPCRH

R/W

H'3F

H'FF86

MSTPCRL

R/W

H'FF

H'FF87

Notes: 1. Lower 16 bits of the address.

2. Registers within the DTC cannot be read or written to directly.

3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.

They cannot be located in external memory space.

When the DTC is used, do not clear the RAME bit in SYSCR to 0.

4. The H8S/2144 Group and H8S/2147N do not include an on-chip DTC, and therefore the

DTCER and DTVECR register addresses should not be accessed by the CPU.

HD6432142 Datasheet(PDF) 225 Page - Renesas Technology Corp

HD6432142 Datasheet(HTML) 225 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL