HD6433636SW datasheet(179/418 Pages) RENESAS

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165

Timer Counter A (TCA)

Bit

76543210

TCA7

TCA6

TCA5

TCA4

TCA3

TCA2

TCA1

TCA0

Initial value

00000000

Read/Write

RRRRRRRR

TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock

source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A

(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive

mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.

TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.

Upon reset, TCA is initialized to H'00.

9.2.3

Timer Operation

Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0,

timer A functions as an 8-bit interval timer.

Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval

timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in

TMA; any of eight internal clock signals output by prescaler S can be selected.

After the count value in TCA reaches H'FF, the next clock signal input causes timer A to

overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt

enable register 1 (IENR1), a CPU interrupt is requested.*

At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as

an interval timer that generates an overflow output at intervals of 256 input clock pulses.

Note: * For details on interrupts, see 3.3, Interrupts.

Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions

as a real-time clock time base by counting clock signals output by prescaler W.

The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods

is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and

prescaler W to their initial values of H'00.

HD6433636SW Datasheet(PDF) 179 Page - Renesas Technology Corp