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HD6433636SW Datasheet(PDF) 212 Page - Renesas Technology Corp |
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HD6433636SW Datasheet(HTML) 212 Page - Renesas Technology Corp |
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212 / 418 page  198 9.4.6 Sample Timer G Application The absolute values of the high and low widths of the input capture signal can be measured by using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9.14 shows an example of this operation. Input capture signal H'FF Input capture register GF Input capture register GR H'00 Counter cleared TCG Figure 9.14 Sample Timer G Application 9.5 Timer Y 9.5.1 Overview Timer Y is a 16-bit up-counter which is incremented by an input clock. Timer Y has two functions: an interval function and an auto-reload function. Features: Features of timer Y are given below: • Choice of eight clocks The clock can be selected from seven internal clocks (ø/8192, ø/2048, ø/512, ø/256, ø/64, ø/16, and ø/4) and an external clock (external event count capability) • An interrupt is requested when the counter overflows |
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