HD6433636SW datasheet(248/418 Pages) RENESAS

248 / 418 page

234

Bit 4: Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred

during asynchronous receiving.

Bit 4: FER

Description

Indicates that data receiving is in progress or has been completed*

(initial value)

[Clearing condition]

After reading FER = 1, cleared by writing 0 to FER

Indicates that a framing error occurred in data receiving

[Setting condition]

The stop bit at the end of receive data is checked and found to be 0*

Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and

keeps its previous state.

2. When two stop bits are used only the first stop bit is checked, not the second. When a

framing error occurs, receive data is transferred to RDR but RDRF is not set. While

FER is set to 1, data receiving cannot be continued. In synchronous mode, data

transmission and reception cannot be performed if FER is set to 1.

Bit 3—Parity Error (PER): Bit 3 is a status flag indicating that a parity error has occurred during

asynchronous receiving.

Bit 3: PER

Description

Indicates that data receiving is in progress or has been completed*

(initial value)

[Clearing condition]

After reading PER = 1, cleared by writing 0 to PER

Indicates that a parity error occurred in data receiving*

[Setting condition]

When the sum of 1s in received data plus the parity bit does not match the

parity mode bit (PM) setting in the serial mode register (SMR)

Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and

keeps its previous state.

2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set.

While PER is set to 1, data receiving cannot be continued. While PER is set to 1 in

synchronous mode, data transmission and reception cannot be performed.

HD6433636SW Datasheet(PDF) 248 Page - Renesas Technology Corp