SH7708 datasheet(569/633 Pages) RENESAS

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17.3.10

Peripheral Module Signal Timing

Table 17.9

Peripheral Module Signal Timing (Conditions: VCC = 3.15–3.6 V, Ta = –20 to

°C)

–60

Module

Item

Symbol

Min

Max

Unit

Figure

TMU,

Timer input setup time

tCLKS

—

17.59

RTC

Timer clock input setup time

tCKS

—

17.60

Timer clock

Single edge

tTCKWH

1.5

—

tcyc

pulse width

Both edges

tTCKWL

2.5

—

tcyc

Oscillation settling time

tROSC

—

17.61

SCI

Input clock

cycle

Asynchronous tScyc

—

tcyc

17.62–17.63

synchronous

—

tcyc

Input clock rise time

tSCKr

—

1.5

tcyc

17.62

Input clock fall time

tSCKf

—

1.5

tcyc

Input clock pulse width

tSCKw

0.4

0.6

tscyc

Transmit data delay time

tTXD

—

100

17.63

Receive data setup time

(synchronous)

tRXS

100

—

Receive data hold time

(synchronous)

tRXH

100

—

Port

Output data delay time

tPORTD

—

17.64

Input data setup time

tPORTS

—

Input data hold time

tPORTH

5—

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