TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

6

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BCENA

85

I

Brightness control enable. When BCENA is low, the brightness control latch is set to the

default value. The output current value in this status is 100% of the setting value by an

external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high,

writing to brightness control latch is enabled.

BLANK

68

I

Blank(light off). When BLANK is high, all the output of the constant current driver is turned

off. The constant current output, which the gray scale data is not zero, is turned on (LED

on) synchronizing to the falling edge of GSCLK after the next rising edge of GSCLK when

BLANK goes from high to low.

BOUT

57

O

Blank signal delay. BOUT is the output with addition of delay time to BLANK.

DCLK

65

I

Clock input for data transfer. The input data is from DIN. All data on the shift register is

selected by RSEL0 and RSEL1, and output data at DOUT is shifted by 1 bit synchronizing

to DCLK. The data except for DOUT is synchronized to the rising edge, and the edge for

data from DOUT is determined by the level of DOMODE.

DIN0 – DIN7

70,71,72,73,

76,77,78,79

I

Input for 8 bit parallel data. These terminals are inputs to the shift register for gray scale

data, brightness control, and OVM. The register selected is determined by RSEL0, 1.

DOMODE

74

I

Timing select for data output. When DOMODE is low, DOUT0–7 is changed synchronizing

to the rising edge of DCLK. When DOMODE is high, DOUT0–7 is changed synchronizing

to the falling edge of DCLK.

DOUT0 – DOUT7

55,54,53,52,

51,49,48,47

O

Output for 8 bit parallel data with 3

for gray scale data, brightness control, and OVM. The register selected is determined by

RSEL0, 1.

GNDANA

43

Analog ground (internally connected to GNDLOG and GNDLED)

GNDLOG

84

Logic ground (internally connected to GNDANA and GNDLED)

GNDLED

5,10,15,20,

29,36,90,96

LED driver ground (internally connected to GNDANA and GNDLOG)

GSCLK

69

I

Clock input for gray scale. The gray scale display is accomplished by lighting LEDs until

the number of GSCLK counted is equal to data latched.

GSOUT

56

O

Clock delay for gray scale. GSOUT is the output with the addition of delay time to GSCLK.

IREF

40

I/O

Constant current value setting. LED current is set to the desired value by connecting an

external resistor between IREF and GND. The 37 times current compares current across

the external resistor sink on the output terminal.

MCENA

46

I

OVM enable. When MCENA is low, the OVM latch is set to the default value. The

comparison voltage in this status is 0.3V. When MCENA is high, writing to the OVM latch

is enabled.

MODE

83

I

8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits

output is selected.

NC

1,2,4,6,9,11,14,16,

19,21,23,24,25,27,

28,30,31,34,35,37,

38,44,50,82,86,88,

89,91,92,95,97,98,

99

No internal connection

OUT0 – OUT15

87,93,94,100,

3,7,8,12,13,

17,18,22,26,

32,33,39

O

Constant current output

RSEL0

RSEL1

66

67

I

Shift register data latch switching. When RSEL1 is low, gray scale data shift register latch

is selected at RSEL0 low, and the brightness control register latch is selected at RSEL0

high. When RSEL1 is high, the OVM register latch is selected at RSEL0 low, and no

register latch is selected at RSEL0 high.