AT90SCR100 datasheet(386/433 Pages) ATMEL

386 / 433 page

386

TPR0327AY–SMS–30Jan09

AT90SCR100

means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-

tem Programming via the JTAG interface. Note that this technique can not be used when using

the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-

icated for this purpose.

During programming the clock frequency of the TCK Input must be less than the maximum fre-

quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input

into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

29.8.1

Programming Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

useful for programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 29-4.

Figure 29-4.

State Machine Sequence to Change the Instruction Word

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

AT90SCR100 Datasheet(PDF) 386 Page - ATMEL Corporation