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ATmega328P Datasheet(PDF) 135 Page - ATMEL Corporation |
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ATmega328P Datasheet(HTML) 135 Page - ATMEL Corporation |
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135 / 345 page  135 7810A–AVR–11/09 ATmega328P [Preliminary] 16.4 Register Description 16.4.1 GTCCR – General Timer/Counter Control Register • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond- ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. Bit 765432 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/Write R/W RRRR R R/W R/W Initial Value 000000 0 0 |
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