ATmega328P datasheet(190/345 Pages) ATMEL

190 / 345 page

190

7810A–AVR–11/09

ATmega328P [Preliminary]

Note:

1. See “USART in SPI Mode” on page 196 for full description of the Master SPI Mode (MSPIM)

operation

• Bits 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Table 19-4.

UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)(1)

Table 19-5.

UPMn Bits Settings

UPMn1

UPMn0

Parity Mode

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

Table 19-6.

USBS Bit Settings

USBSn

Stop Bit(s)

01-bit

12-bit

ATmega328P Datasheet(PDF) 190 Page - ATMEL Corporation