ATmega328P datasheet(236/345 Pages) ATMEL

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236

7810A–AVR–11/09

ATmega328P [Preliminary]

In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Han-

dling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK

bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the 2-wire Serial Bus.

21.9.5

TWAR – TWI (Slave) Address Register

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of

TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,

and not needed in the Master modes. In multi master systems, TWAR must be set in masters

which can be addressed as Slaves by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

21.9.6

TWAMR – TWI (Slave) Address Mask Register

• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can

mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 21-22 shown the address match logic in

detail.

Bit

(0xBA)

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

TWAR

Read/Write

R/W

Initial Value

Bit

(0xBD)

TWAM[6:0]

–

TWAMR

Read/Write

R/W

Initial Value

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