ATmega16A datasheet(109/352 Pages) ATMEL

109 / 352 page

109

8154B–AVR–07/09

ATmega16A

Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

16.11 Register Description

16.11.1

TCCR1A – Timer/Counter1 Control Register A

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-

tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OC1A or OC1B pin must be set in order to enable the output driver.

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

COM1A1

COM1A0

COM1B1

COM1B0

FOC1A

FOC1B

WGM11

WGM10

TCCR1A

Read/Write

R/W

Initial Value

ATmega16A Datasheet(PDF) 109 Page - ATMEL Corporation

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