ATmega32A datasheet(127/352 Pages) ATMEL

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8155B–AVR–07/09

ATmega32A

17.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM2[1:0] = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC2) is cleared on the compare match

between TCNT2 and OCR2 while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM

mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 17-7.

The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.

Figure 17-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-

put can be generated by setting the COM21:0 to 3 (see Table 17-5 on page 134). The actual

OC2 value will only be visible on the port pin if the data direction for the port pin is set as output.

The PWM waveform is generated by clearing (or setting) the OC2 Register at the compare

match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the

OC2 Register at compare match between OCR2 and TCNT2 when the counter decrements. The

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

ATmega32A Datasheet(PDF) 127 Page - ATMEL Corporation