ATmega32A datasheet(157/352 Pages) ATMEL

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8155B–AVR–07/09

ATmega32A

The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift

The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writing a one to its bit location. The TXC Flag is useful in half-duplex

communication interfaces (like the RS485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit

Complete Interrupt will be executed when the TXC Flag becomes set (provided that global inter-

rupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine

does not have to clear the TXC Flag, this is done automatically when the interrupt is executed.

19.6.4

Parity Generator

The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPM1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

19.6.5

Disabling the Transmitter

The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing

and pending transmissions are completed, i.e., when the transmit Shift Register and transmit

Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no lon-

ger override the TxD pin.

19.7

Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis-

ter to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden

by the USART and given the function as the receiver’s serial input. The baud rate, mode of oper-

ation and frame format must be set up once before any serial reception can be done. If

synchronous operation is used, the clock on the XCK pin will be used as transfer clock.

19.7.1

Receiving Frames with 5 to 8 Data Bits

The receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCK clock, and shifted into the receive Shift Register until

the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When

the first stop bit is received, i.e., a complete serial frame is present in the receive Shift Register,

the contents of the Shift Register will be moved into the receive buffer. The receive buffer can

then be read by reading the UDR I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant

ATmega32A Datasheet(PDF) 157 Page - ATMEL Corporation