ATmega32A datasheet(177/352 Pages) ATMEL

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177

8155B–AVR–07/09

ATmega32A

20.2.1

TWI Terminology

The following definitions are frequently encountered in this section.

20.2.2

Electrical Interconnection

As depicted in Figure 20-1, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line

high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any

bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 300. Two

different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,

and one valid for bus speeds up to 400 kHz.

20.3

Data Transfer and Frame Format

20.3.1

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 20-2. Data Validity

20.3.2

START and STOP Conditions

The master initiates and terminates a data transmission. The transmission is initiated when the

master issues a START condition on the bus, and it is terminated when the master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

Table 20-1.

TWI Terminology

Term

Description

Master

The device that initiates and terminates a transmission. The master also generates the

SCL clock.

Slave

The device addressed by a master.

Transmitter

The device placing data on the bus.

Receiver

The device reading data from the bus.

SDA

SCL

Data Stable

Data Change

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