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ATmega64A Datasheet(PDF) 389 Page - ATMEL Corporation |
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ATmega64A Datasheet(HTML) 389 Page - ATMEL Corporation |
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389 / 392 page ![]() v 8160C–AVR–07/09 ATmega64A 23.5 Prescaling and Conversion Timing ................................................................236 23.6 Changing Channel or Reference Selection ...................................................239 23.7 ADC Noise Canceler .....................................................................................241 23.8 ADC Conversion Result .................................................................................245 23.9 Register Description ......................................................................................247 24 JTAG Interface and On-chip Debug System ...................................... 252 24.1 Features ........................................................................................................252 24.2 Overview ........................................................................................................252 24.3 TAP – Test Access Port ................................................................................252 24.4 TAP Controller ...............................................................................................255 24.5 Using the Boundary -scan Chain ...................................................................256 24.6 Using the On-chip Debug system ..................................................................256 24.7 On-chip Debug Specific JTAG Instructions ...................................................257 24.8 Using the JTAG Programming Capabilities ...................................................258 24.9 On-chip Debug Related Register in I/O Memory ...........................................258 24.10 Bibliography ...................................................................................................258 25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259 25.1 Features ........................................................................................................259 25.2 Overview ........................................................................................................259 25.3 Data Registers ...............................................................................................259 25.4 Boundary-scan Specific JTAG Instructions ...................................................261 25.5 Boundary-scan Chain ....................................................................................262 25.6 ATmega64A Boundary-scan Order ...............................................................273 25.7 Boundary-scan Description Language Files ..................................................280 25.8 Boundary-scan Related Register in I/O Memory ...........................................280 26 Boot Loader Support – Read-While-Write Self-programming ......... 281 26.1 Features ........................................................................................................281 26.2 Overview ........................................................................................................281 26.3 Application and Boot Loader Flash Sections .................................................281 26.4 Read-While-Write and No Read-While-Write Flash Sections ........................282 26.5 Boot Loader Lock Bits ...................................................................................284 26.6 Entering the Boot Loader Program ................................................................285 26.7 Addressing the Flash During Self-programming ............................................286 26.8 Self-programming the Flash ..........................................................................287 26.9 Register Description ......................................................................................293 |
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