HT66F30 datasheet(122/224 Pages) HOLTEK

122 / 224 page

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

Rev. 1.00

122

November 3, 2009

CCRP

CCRA

Counter

Value

Counter Cleared by CCRP

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

TPnA Pin

TnAOC = 1

TnON bit

Duty Cycle

set by CCRA

PWM Period

set by CCRP

TnAI O1, TnAI O0 = 10 PWM Out put

TnAIO1, TnAIO0 = 00

Output Inactive

TnAIO 1, TnAIO 0 = 10

Interrupt

st ill generated

Here TnAIO1,

TnAIO 0 = 00

O utput is Inactive

PWM runs int ernally

TnAIO1, TnAIO0 = 10

Resume PWM Output

Counter Stops

if TnO N bit low

Count er reset

when TnON

ret urns high

PWM resumes

operat ion - outputs remain

at same level

Time

TnCCLR = 0;

Mode Bits TnA(B)M1, TnA(B)M0 = 10

TnPWM1/TnPWM0 = 00

TnAPOL bit

Output Inverts

When TnAPOL = 1

TPnB Pin

TnBOC = 0

TnPAU bit

Resume

Paus e

CCRB

CCRB Int.

Flag TnBF

TPnB Pin

TnBOC = 1

Duty Cycle

set by CCRB

PWM Mode

- Edge Aligned

Note:

1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period

2. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01

3. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty

HT66F30 Datasheet(PDF) 122 Page - Holtek Semiconductor Inc

HT66F30 Datasheet(HTML) 122 Page - Holtek Semiconductor Inc

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