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HT68F20 Datasheet(PDF) 120 Page - Holtek Semiconductor Inc |
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HT68F20 Datasheet(HTML) 120 Page - Holtek Semiconductor Inc |
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120 / 210 page ![]() HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Rev.1.00 120 November 3, 2009 CCRP CCRA CCRA Int. Flag TnAF CCRP Int. Flag TnPF TPnA Pin TnAOC = 1 TnON bit Duty Cycle set by CCRA PW M Period set by CCRP TnAI O1, TnAI O0 = 00 Out put Inactive Counter Stops if TnON bit low Counter reset when TnON ret urns high Time TnAPOL bit Out put Inverts When TnAPOL = 1 TPnB Pin TnBOC = 0 TnPAU bit Resume Pause CCRB CCRB Int. Flag TnBF TPnB Pin TnBOC = 1 Duty Cycle set by CCRB TnAIO1, TnAIO0 = 10 PWM Output TnAI O1, TnAI O0 = 10 PWM O utput Counter Value TnCCLR = 0; Mode Bits TnA(B)M1, TnA(B)M0 = 10 TnPWM1/TnPWM0 = 11 PWM Mode - Centre Aligned Note: 1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01 4. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty |
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