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HT66F20 Datasheet(PDF) 117 Page - Holtek Semiconductor Inc

Part # HT66F20
Description  Enhanced A/D Flash Type MCU 8-Bit MCU with EEPROM
PDF  250 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT66F20 Datasheet(HTML) 117 Page - Holtek Semiconductor Inc

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HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
Rev. 1.20
117
June 4, 2010
¨ TM1BL Register - 10-bit ETM
Bit
76543210
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
00000000
Bit7~0
TM1BL: TM1 CCRB Low Byte Register bit 7~bit 0
TM1 10-bit CCRB bit 7~bit 0
¨ TM1BH Register - 10-bit ETM
Bit
76543210
Name
¾¾¾¾¾¾
D9
D8
R/W
¾¾¾¾¾¾
R/W
R/W
POR
¾¾¾¾¾¾
00
Bit 7~2
Unimplemented, read as
²0²
Bit 1~0
TM1BH: TM1 CCRB High Byte Register bit 1~bit 0
TM1 10-bit CCRB bit 9 ~ bit 8
Enhanced Type TM Operating Modes
The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output
Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using
the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register.
ETM Operating Mode
CCRA Com-
pare Match
Output Mode
CCRA
Timer/Coun-
ter Mode
CCRA PWM
Output Mode
CCRA Single
Pulse Output
Mode
CCRA Input
Capture
Mode
CCRB Compare Match Output Mode
ÖÖÖ
¾
¾
CCRB Timer/Counter Mode
ÖÖÖ
¾
¾
CCRB PWM Output Mode
ÖÖÖ
¾
¾
CCRB Single Pulse Output Mode
¾
¾
¾Ö¾
CCRB Input Capture Mode
Ö
Ö
Ö¾Ö
Compare Output Mode
To select this mode, bits TnAM1, TnAM0 and TnBM1,
TnBM0 in the TMnC1/TMnC2 registers should be all
cleared to zero. In this mode once the counter is en-
abled and running it can be cleared by three methods.
These are a counter overflow, a compare match from
Comparator A and a compare match from Comparator
P. When the TnCCLR bit is low, there are two ways in
which the counter can be cleared. One is when a com-
pare match occurs from Comparator P, the other is when
the CCRP bits are all zero which allows the counter to
overflow. Here both the TnAF and TnPF interrupt re-
quest flags for Comparator A and Comparator P respec-
tively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated.



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